FIG. 1 is a circuit schematic of a typical NAND Flash memory cell string used in memory cell array. The cell string has a bit line BL connected with a string select transistor 12, wherein the gate of the string select transistor 12 is connected to a string select line, SSL. The cell string also includes a plurality of serially connected floating gate memory cells 16 each connected to respective wordlines WL0 to WLn, and a ground select transistor 14 connected to a ground select line, GSL. The GSL transistor 14 is disposed between the common source line 18 and the last floating gate memory cell 16. When erased, the memory cell will have a negative threshold and be set to a default logic state, such as logic “1”, for example. When written, another way called programmed, the memory cell will have its threshold voltage changed to positive, thus representing the opposite “0” logic state. The stored logic state of a memory cell might be changed unintentionally while programming other cells on the same wordline. Generally, a program inhibit scheme is used to reduce the disturbance to a non-programmed memory cell 16 on a biased wordline but an effective solution is still not seen.